Logic-based processing devices form an integral part of many modern electronic devices. In order to create innovative electronic devices with ever-increasing performance standards, there is a constant effort to improve the speed and efficiency of logic-based processing devices. Generally, a logic-based processing device includes several design, testing, verification, and validation stages throughout the manufacturing process. First, a logic-based processing device is designed through the use of one or more software design tools. The functionality of the logic-based processing device design is then verified using additional software in what is known as a pre-silicon verification process. The pre-silicon verification process allows a manufacturer to detect and fix bugs in the logic architecture of the logic-based processing device before manufacturing. Next, one or more prototypes of the logic-based processing device are manufactured, and subsequently tested in what is known as a post-silicon validation process. Post-silicon validation is used to detect bugs not only in the logic architecture of the logic-based processing device, but also from manufacturing process variations or other environmental issues. Upon fixing any detected bugs, the logic-based processing device can then be manufactured on a large scale.
Pre-silicon verification and post-silicon validation are crucial steps in the design, test, and manufacturing of integrated circuits. As discussed above, pre-silicon verification allows a manufacturer to detect and correct bugs in one or more parts of a logic-based processing device before it is manufactured, thereby saving time and money. During pre-silicon verification, a virtualized logic-based processing device including one or more inputs and one or more outputs is loaded into a verification system such as a simulator, simulation accelerator, or emulator. A variety of tests are then run on the design of the logic-based processing device in order to detect bugs (i.e., design flaws) in the circuit design. The tests generally supply input data to the inputs of the logic-based processing device and perform checks on the behavior of the logic-based processing device. If the behavior of the logic-based processing device differs from what is expected given the input data, an error is detected.
When an error is detected, the bug that caused the error is debugged in order to determine the root cause and location of the error in the logic circuitry or other components of the logic-based processing device. Localization allows a designer to find and correct the bug. One problem with pre-silicon verification arises due to error detection latency, which is the time between the occurrence of an error due to a bug and the detection of the error by a test. Bugs with error detection latencies longer than a few thousand clock cycles are highly challenging to localize due to the large number of intervening instructions executed by the logic-based processing device between the time the error occurs and the detection of the error. In other words, due to the large error detection latency, it is extremely difficult to trace back in history to the origin of the detected error. Accordingly, a pre-silicon verification process is needed that is capable of detecting errors with a low error detection latency.
Post-silicon validation is similar to pre-silicon verification, but occurs on one or more prototypes of a logic-based processing device that have been physically manufactured. Post-silicon validation is essentially the real world counterpart to pre-silicon verification, allowing manufacturers to detect bugs attributable not only to the architecture of the logic-based processing device, but also due to process variations, manufacturing defects, and environmental issues. Generally, pre-silicon verification alone is inadequate to fully vet a logic-based processing device, as it is often too slow and incapable of detecting bugs that may only occur after the logic-based processing device is manufactured. Failure to detect such bugs may be incredibly costly to a manufacturer, who may be left with a large inventory of inferior or inoperable logic-based processing devices. Accordingly, pre-silicon verification and post-silicon validation are often used together in order to adequately test a logic-based processing device.
Conventional post-silicon validation approaches have often been ad-hoc, focusing on the manual creation of test programs based on heuristics such as designer knowledge. Such an approach is not only time consuming, but costly as well. Further, as the complexity of logic-based processing devices continues to increase, so does the difficulty of creating reliable and robust post-silicon validation tests. Generally, the crux of post-silicon validation tests is not the detection of errors, but rather the localization of the bugs that caused a detected error. Previous efforts to localize bugs during post-silicon validation have focused on either simulation to obtain an expected response, or failure reproduction, which involves returning the system to an error-free state and re-running the system with the exact input stimuli to reproduce the failure. Simulation is orders of magnitude slower than running a physical test on the logic-based processing device itself, while failure reproduction is often difficult due to intermittency in the detected error because of uncontrollable factors such as asynchronous inputs or outputs and multiple-clock domains.
Further, conventional approaches to post-silicon validation suffer from the same error detection latency problems as discussed above with respect to pre-silicon verification. That is, it may take several billion clock cycles between the occurrence of an error and the detection thereof. As a result, processes for pre-silicon verification and post-silicon validation are needed that are capable of consistently detecting errors with a decreased error detection latency, while being cost effective and easy to generate.